About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEEE T-ED
Paper
An Advanced High-Performance Trench-Isolated Self-Aligned Bipolar Technology
Abstract
This paper describes the extension of “double-poly” self-aligned bipolar technology to include a silicon-filled trench with self-aligned cap oxide isolation, a p<sup>+</sup> polysilicon defined epi-base lateral p-n-p, a p<sup>+</sup> polysilicon defined self-aligned guard-ring Schottky-barrier diode, and p<sup>+</sup> polysilicon resistors. Experimental circuits designed with 1.2-µm design rules have shown switching delays of as small as 73 ps for ECL circuits with FI = FO = 1. ISL circuits built with the same process on the same chip as the ECL circuits exhibit a sub-400-psswitching delay. The performance of the technology has also been demonstrated by a 5-kbit ECL SRAM with a 760-µm<sup>2</sup> Schottky-clamped multi-emitter cell and 1.0-ns access time. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.