23 ps/2.1 mW ECL gate

Abstract

Simulated output waveforms at 0.1-, 0.3 and, 0.6-pF loading of a design optimized for a 0.3-pF nominal load are shown. An AC-coupled APD ECL (active-pull-down emitter-coupled-logic) gate with significantly improved gate delay in the low-power (1-2 mW) regime is described. Unloaded gate delays of 23 and 35 ps at 2.1- and 1.1-mW/gate power, respectively, were demonstrated in a bipolar technology using a double-poly, self-aligned process with emitter width of 0.8 μm (mask). The device cross section is presented along with an SEM (scanning electron microscopy) micrograph of the basic gate used in the ring oscillator.