ISSCC 2023
Conference paper

An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches


This work presents a single-stage, calibration-free, 8-bit, time-domain ADC designed in a 5nm CMOS that achieves 16.6fJ/conv-step FoM with 313μm2 area. The digital intensive architecture runs at 1GS/s and 1.25GS/s with 0.7V and 0.8V supply, respectively. The proposed ADC introduces: 1) a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the reference voltage and to allow a wide input swing of 0.75Vppd; 2) 2x interpolating sense-amplifier-latches (SAL) to reach a sub-gate delay of 2.3ps in a power and area efficient manner; and 3) redundancy to accommodate possible wrong decisions of the sign bit comparator allowing a minimum size design without any calibration.