In this paper, we describe methods and techniques used to verify the IBM POWER9 microprocessor in the context of heterogeneous and open system structures. The base concepts for the functional verification are those that have been already used in IBM POWER7 and IBM POWER8 verification. However, the POWER9 design point provided new features to connect to accelerator chips for cognitive or other use cases. These features required innovative verification solutions. The examples given in this paper demonstrate how a combination of new tools and new forms of collaboration addressed these verification challenges.