A semi-custom voltage-island technique and its application to high-speed serial links [CMOS active power reduction]

Abstract

Supply-voltage reduction is a known technique for reducing CMOS active power. We propose a semi-custom voltage-island approach based on internal regulation and selective custom design. This approach enables transparent embedding, since no additional external power supply is needed. We apply the approach to high-speed serial links, and we show that high performance is retained through targeted application of custom circuit and logic design. A chip is presented that evaluates the presented approach on a 3000 gate 3.2 Gbps multi-protocol serial-link receiver logic core. When reducing the supply from 1.2 V to 0.95 V, the chip demonstrates power savings of over 25%.