Kangguo Cheng, Chanro Park, et al.
VLSI Technology 2020
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges for GAA nanosheet FETs are reviewed and discussed. Finally, an analysis of future innovations required to continue scaling nanosheet FETs and future technologies is discussed.
Kangguo Cheng, Chanro Park, et al.
VLSI Technology 2020
Ruqiang Bao, Reinaldo A. Vega, et al.
IEDM 2019
Miaomiao Wang, Jingyun Zhang, et al.
IRPS 2019
Huimei Zhou, Miaomiao Wang, et al.
IRPS 2022