About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IEEE International SOI Conference 1999
Conference paper
A dynamic body discharge technique for SOI circuit applications
Abstract
It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-Vt floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.