ISSCC 1992
Conference paper

A 5Gb/s 16×16 Si-bipolar crosspoint switch

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An experimental 16×16, nonblocking, asynchronous crosspoint switch with 5 Gb/s channel data rate is described. Implemented in a 0.8-μm, double-poly, self-aligned Si-bipolar ECL (emitter coupled logic) technology, the 3×3 mm2 chip with a multiplexer-type architecture and a three-device crosspoint cell features a data path delay of 420 ps and a set-up time of 1 ns, and dissipates about 4.6 W. Signal levels are ECL compatible. This crosspoint which supports selective or full broadcasting and a simple expansion mechanism.