Eric J. Fluhr, Steve Baumgartner, et al.
IEEE JSSC
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Eric J. Fluhr, Steve Baumgartner, et al.
IEEE JSSC
Phillip J. Restle, Craig A. Carter, et al.
Digest of Technical Papers-IEEE International Solid-State Circuits Conference
Alberto Valdes-Garcia, Fengnian Xia, et al.
IMS 2013
Keith A. Jenkins, Walter H. Henkels
IEEE Journal of Solid-State Circuits