Keith A. Jenkins, John D. Cressler
IEEE T-ED
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Keith A. Jenkins, John D. Cressler
IEEE T-ED
Joachim N. Burghartz, Jean-Olivier Plouchart, et al.
IEEE Electron Device Letters
Albert J. Fixl, Keith A. Jenkins
Microelectronic Engineering
Keith A. Jenkins
IEEE SSC-L