Chirag S. Patel, Paul S. Andry, et al.
IITC 2005
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Chirag S. Patel, Paul S. Andry, et al.
IITC 2005
Keith A. Jenkins, Byungdu Oh
Journal of Applied Physics
Albert J. Fixl, Keith A. Jenkins
Microelectronic Engineering
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VLSI Circuits 2003