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IEEE Electron Device Letters
A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 µm. © 2000, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
Shu-Jen Han, Satoshi Oida, et al.
IEEE Electron Device Letters
Keith A. Jenkins, James P. Eckhardt
IEEE Design and Test of Computers
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IEEE Journal of Solid-State Circuits