A 10 nm MOSFET concept

Abstract

In the present work we describe a concept for the fabrication of a 10 nm MOSFET. The combination of an epitaxial silicon structure based on SOI with an anisotropic etch allows the definition of ultra-short channel devices. By cutting through a highly doped n++ layer on top of an undoped channel layer using a KOH-etch, source and drain as well as the channel itself are defined in one step. Since the etch produces a V-like groove, an extremely small source/drain separation - defined by the tip region of the V - can be obtained. We claim that even standard optical lithography can be used in principle to generate channels of around 10 nm length. Measured output characteristics on first prototypes indicate the possibility of using the proposed concept to generate functioning MOSFETs with acceptable short-channel effects. © 2001 Elsevier Science B.V.