Arun Natarajan, Scott K. Reynolds, et al.
IEEE Journal of Solid-State Circuits
A 40-Gb/s packaging solution that uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is presented. Since such a high speed was beyond the reach of conventional package designs, a new design methodology was proposed-discontinuity cancellation in both signal-current and return-current paths. The 3-D structures of bonding wires, vias, solder ball pads, and power distribution networks were optimized for the discontinuity cancellation. Two versions of four-layer WB-PBGA packages were designed; one according to the proposed methodology and the other conventionally. The proposed design methodology was verified with full-wave simulation, passive bandwidth measurement, time domain reflectometry (TDR), eye diagram measurement, and jitter analysis. © 2008 IEEE.
Arun Natarajan, Scott K. Reynolds, et al.
IEEE Journal of Solid-State Circuits
Dong Gun Kam, Joungho Kim
IEEE Transactions on CPMT
Jongjoo Shim, Dong Gun Kam, et al.
IEEE Trans Electromagn Compat
Dong Gun Kam, Duixian Liu, et al.
IEEE Transactions on CPMT