3D integrated water cooling of a composite multilayer stack of chips

Abstract

New generation supercomputers with three dimensional stacked chip architectures pose a major challenge with respect to removal of dissipated heat which can reach currently as high as 250 W/cm2 in multilayer chip stacks of less than 0.3 cm3 volume. Interlayer integrated water cooling [1]is a very promising approach for such high heat flux removal due to much larger thermal capacity and conductivity of water compared to air, the traditional cooling fluid. In the current work, a multiscale conjugate heat transfer model is developed for integrated water cooling of chip layers and validated with experimental measurements on a specially designed thermal test vehicle that simulates a four tier chip stack with a footprint of 1 cm 2. The cooling heat transfer structure, which consists of microchannels with cylindrical pin fins, is conceived in such a way that it can be directly integrated with the device layout in multilayer chips. Every composite layer is cooled by water flow in microchannels (height: 100 μm), which are arranged in 2 port water inlet-outlet configuration. The total power removed in the stack is 390 W at a temperature gradient budget of 60 K from liquid inlet to maximal junction temperature, corresponding to about 1.3 kW/cm3 volumetric heat flow. The computational cost and complexity of detailed CFD modeling of heat transfer in stacked chips with integrated cooling can be prohibitive. Therefore, the heat transfer structure is modeled using a porous medium approach, where the model parameters of heat transfer and hydrodynamic resistance are derived from averaging the results of the detailed 3D-CFD simulations of a single stream-wise row of fins. The modeling results indicate that an isotropic porous medium model does not accurately predict the measured temperature fields. The variation of material properties due to temperature gradients are found to be large, therefore variable properties are used in the model. It is also shown that the modeling of the heat transfer in the cooling sublayers requires the implementation of a porous medium approach with a local thermal non-equilibrium as well as orthotropic heat conduction and hydrodynamic resistance. The improved model reproduces the temperatures measured in the stack within 10%. The model is used to predict the behavior of multilayer stacks mimicking the change of heat fluxes resulting from variations in the computational load of the chips during their operation. © 2010 by ASME.