ISTFA 2013
Conference paper

32nm CMOS SOI test site for emission tool evaluation


We describe a test chip designed and fabricated in 32nm CMOS SOI. The test chip was developed to assist in the characterization and testing of hot electron emission based test systems for both existing and forthcoming technology nodes, and contains circuit structures of increasing density and complexity. We also describe some unique circuit functions that may be of use in other applications. Copyright © 2013 ASM International® All rights reserved.