An n-channel single-level polysilicon, 25 nm gate-oxide technology, using electron-beam lithography with a minimum feature size of 1 µm has been implemented for MOSFET logic applications. The six-mask process employs semirecessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques, and reactive ion etching. A description of the process is given, with particular emphasis on topographical considerations. Implementation of a field etch-back after source/drain implant to eliminate a low thick-oxide parasitic-device threshold is also discussed. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.