Program Day 3 - Thursday 17/11/2016
09:00 - 10:00 Keynote: miTLS: Can cryptography, formal methods, and applied security be friends?
Dr. Markulf Kohlweiss, Researcher, Microsoft Research
Session Chair: Sharon Keidar-Barner
10:00-11:15 Technical session: Software Verification
Session chair: Nikolaj Bjorner
Formula Slicing: Inductive Invariants from Preconditions,
Egor George Karpenkov and David Monniaux
Advancing software model checking beyond linear arithmetic theories,
Ahmed Mahdi, Karsten Scheibler, Felix Neubauer, Martin Fränzle and Bernd Becker
Predator Shape Analysis Tool Suite,
Lukas Holik, Michal Kotoun, Petr Peringer, Veronika Šoková, Marek Trtík and Tomas Vojnar
11:15 - 12:00 Coffee Break
12:00 - 13:30 Special Industry Session
Session chair: Merav Aharoni
Challenges and Opportunities in System Validation and Debug: a Collaborative Approach,
Aviv Barkai, Intel
Over the last year, there has been renewed interest in creating a collaborative effort, including several companies as well as academia, specifically on topics such as:
1) Using design for test (DFT) for system debug
2) Defining standard test suites
3) Defining validation data analytics
4) Coverage definition, measurement and interpretation
The System Validation and Debug Technology Committee (SVDTC) is an IEEE-CEDA committee that brings together experts from industry and academia to address these issues, specifically for on-silicon platforms. In my talk, I will describe the challenges and work done within this organization.
SVA for FV: Beyond Assertions,
Max Chvalevsky, Marvell
Testing Big Data Systems,
Akram Bitar, IBM Research - Haifa
13:30 - 15:00 Lunch
15:00 - 16:00 HVC Award Ceremony & presentation
Session chair: Roderick Bloem
16:00 Closing remarks
Keynote Speakers
- Prof. Swarat Chaudhuri, Rice University
- Dr. Markulf Kohlweiss, Researcher, Microsoft Research
- Dr. Rajeev K. Ranjan, Senior Group Director, R&D Formal and Automated verification, Cadence
- Prof. Andreas Veneris, University of Toronto