Keynote Speakers
Title: Current Trends and Future Direction in Eco-system of Hardware Formal Verification: A Technical and Business Perspective
Dr. Rajeev K. Ranjan, Senior Group Director, R&D Formal and Automated verification, Cadence
Hardware formal verification is increasingly being adopted in the modern SoC design and verification flow for architectural specification and verification through RTL development and debugging through SoC integration -- all the way up to post-silicon debugging. The productivity and quality benefits of adopting this technology for a gamut of verification tasks are well established. In this talk, we will cover the current trends and future directions in this area that is shaped by the technical feasibility of the solutions and the business RoI seen by different stakeholders – chip companies, design/verification engineers, formal EDA vendors, and formal solution development engineers.
Speaker Bio
Rajeev Ranjan is leading the business development efforts of a newly formed business unit at Cadence following the acquisition of Jasper Design Automation, where he was the CTO and was responsible for developing Jasper's overall technology vision and driving the business value of formal.
Rajeev has been active in the area of formal verification for over 20 years. He has served in the organization and program committee of many international conferences including DAC, ICCAD, FMCAD, and CHARME. He has published numerous articles and has 15 patents in the area of functional verification. Rajeev received his Bachelor's degree from Indian Institute of Technology, Kanpur (aka IIT Kanpur), his Master's degree from University of Illinois at Urbana-Champaign (aka UIUC), and his doctorate degree from University of California at Berkeley (aka UC Berkeley). He also has an MBA degree from Wharton School of Business with a focus on entrepreneurial management and finance.
Keynote Speakers
- Prof. Swarat Chaudhuri, Rice University
- Dr. Markulf Kohlweiss, Researcher, Microsoft Research
- Dr. Rajeev K. Ranjan, Senior Group Director, R&D Formal and Automated verification, Cadence
- Prof. Andreas Veneris, University of Toronto