Keynote Speakers
Title: Bug Wars: Automation Awakens
Prof. Andreas Veneris, Dept. of Electrical and Computer Engineering, and Dept. of Computer Science, University of Toronto
Verification is the undisputed bottleneck in the design cycle consuming two thirds of the total chip development effort. This is in part because of the complexity of modern designs, the impact of geographical dispersed teams integrating new components with third-party/legacy IP under tight time-to-market goals, the evolving role of verification engineers to not only discover bugs but also aid correct them and the ever-evolving nature of the task itself. Today verification has stretched itself beyond its traditional boundaries into validation as most of silicon re-spins are not due to physical defects but because of functional errors not discovered or fixed earlier in the design cycle. Although parts of verification have been automated the core issue driving this gap remains debugging as it consumes more than half of the overall effort being a predominantly manual task.
In this talk, we revisit automation efforts in functional debug from late 1980s, when it was first introduced, to recent formal advances placing it into context as we recount new directions. In more detail, we will first outline early methodologies stemming from test and fault diagnosis to more recent techniques based on Boolean satisfiability. We will examine different angles of the debug problem and respective solutions for its various manifestations in the verification cycle. This will allow us to appraise theoretical and practical parallels in the foundations of those two tasks. As we evaluate the progress in debug automation, we will point out emerging deficiencies of existing methodologies more notably during regression verification. To that end, we will present novel techniques in debugging triage where statistical solutions, a radical departure from existing debug efforts, need complement traditional simulation/formal methods to not only take into account the design response but also the human factor. We will conclude with a mantra that research in debugging in the past 30 years points to a direction where verification and test prove once again to be fields deeply intertwined, and we will provide guidance for methodologies in silicon debug rooted on existing functional debug procedures.
Speaker Bio
Andreas Veneris received a Diploma in Computer Engineering and Informatics from the University of Patras in 1991, the M.S. degree in Computer Science from the University of Southern California, Los Angeles in 1992 and the Ph.D. degree in Computer Science from the University of Illinois at Urbana-Champaign in 1998. In 1998-99 he was a visiting faculty at the University of Illinois. He joined the University of Toronto in 1999 where today he is a Professor of Electrical and Computer Engineering cross-appointed with the Department of Computer Science. His research interests include algorithms and CAD tools for debug, verification, synthesis and test of digital systems and circuits, applications of machine learning in EDA, theoretical computer science and crypto-finance . He received a best paper award in ASP-DAC 2001 and a 10-year Retrospective Best Paper award in ASP-DAC 2014. He has been nominated for two best paper awards in DATE 2007 and ASP-DAC 2010, he has co-authored one book and he holds three patents. As a Fellow of the Japanese Society for the Promotion of Science he was an Adjunct Faculty at the University of Tokyo in 2010-11. In the past, he was also visiting faculty at the Athens University of Economics and Business. Andreas is a member of IEEE, ACM, AMS, AAAS, Technical Chamber of Greece, Professional Engineers of Ontario and The Planetary Society.
Keynote Speakers
- Prof. Swarat Chaudhuri, Rice University
- Dr. Markulf Kohlweiss, Researcher, Microsoft Research
- Dr. Rajeev K. Ranjan, Senior Group Director, R&D Formal and Automated verification, Cadence
- Prof. Andreas Veneris, University of Toronto