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IBM's Verification Track 2005
November 13, 2005
Organized by IBM Research Lab in Haifa, Israel
Invitation
The Software and Verification Technologies Department at the IBM Haifa Research Lab (HRL) cordially invites you to a full-day seminar on verification, which is part of a verification conference that includes verification technologies, software testing, and PADTAD.
This is the sixth in a sequence of verification seminars held by HRL since 1999.
The seminar will take place on Sunday, the 13th of November, 2005 at the IBM Haifa Labs site on the University of Haifa campus, in the Auditorium (room L100), from 9:30 to 17.15. Lunch and light refreshments will be served. A detailed program is available. Participation is free.
Please confirm your participation, via the seminar website:
http://www.haifa.il.ibm.com/Workshops/verification2005/registration.html
Verification Track Topics
- Microprocessors, ASICs, SOCs, and system verification
- Experiences with simulation based and formal verification
- Classification of hardware bugs
- High-level test generation for functional verification
- Simulation based verification
- Use of PSL - methodologies and experiences
- Emulation and acceleration techniques in verification
- Post silicon debugging
- Formal methods and their applications
- Verification using SAT
- Verification coverage
- Equivalence checking
- Path analysis for verification
- Design for verifiability
- Hardware/software co-verification and co-testing
- Use of ESL methods for verification.
- Simulation-checking: assertion based, high-level rule-based, reference models and score-boards
- CSP applications in functional verification
- Hybrid simulation and formal analysis methods
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