The circuits and physical design of the synergistic processor element of a CELL processorO. TakahashiR. Cooket al.2005VLSI Circuits 2005
4.0GHz 0.18.μm CMOS PLL based on an interpolative oscillatorFadi H. GebaraJeremy D. Schaubet al.2005VLSI Circuits 2005
A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technologyThomas ToiflChristian Menolfiet al.2005VLSI Circuits 2005