SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 psM. KhaterJ.-S. Riehet al.2004IEDM 2004
Interface engineering for enhanced electron mobilities in W/HfO 2 gate stacksA.C. CallegariP. Jamisonet al.2004IEDM 2004
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturingH.S. YangR. Maliket al.2004IEDM 2004
Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakageE. GusevC. Cabral Jr.et al.2004IEDM 2004
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)J. CaiK. Rimet al.2004IEDM 2004
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyondD. FriedJ. Hergenrotheret al.2004IEDM 2004
Charge trapping in aggressively scaled metal gate/high-κ stacksE. GusevV. Narayananet al.2004IEDM 2004