A 0.039um2 high performance eDRAM cell based on 32nm high-K/metal SOI technology
- Nauman Z. Butt
- Kevin McStay
- et al.
- 2010
- IEDM 2010
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2 results for Todd Weaver
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
- John Barth
- Don Plass
- et al.
- 2012
- VLSI Circuits 2012