A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
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7 results for A. Arceo
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
Development of TiO2 containing hardmasks through PEALD deposition
- Anuja De Silva
- Indira Seshadri
- et al.
- 2017
- SPIE Advanced Lithography 2017
Development of TiO2 containing hardmasks through plasma-enhanced atomic layer deposition
- Anuja De Silva
- Indira Seshadri
- et al.
- 2017
- J. Micro/Nanolithogr. MEMS MOEMS
Study of alternate hardmasks for extreme ultraviolet patterning
- Anuja De Silva
- Indira Seshadri
- et al.
- 2016
- JVSTB