A software-assisted peak current regulation scheme to improve power-limited inference performance in a 5nm AI SoCMonodeep KarJoel Silbermanet al.2024ISSCC 2024
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Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural NetworksSidney TsaiPritish Narayananet al.2023ISCAS 2023
Architecture and Programming of Analog In-Memory-Computing Accelerators for Deep Neural NetworksSidney TsaiPritish Narayananet al.2024IPDPS 2024