1 Mb 0.41 μm2; 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert K. Montoye
- et al.
- 2014
- IEEE JSSC
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59 results for Leland Chang
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
- Jinwook Oh
- Sae Kyu Lee
- et al.
- 2020
- VLSI Circuits 2020
Memory and Interconnect Optimizations for Peta-Scale Deep Learning Systems
- Swagath Venkataramani
- Vijayalakshmi Srinivasan
- et al.
- 2019
- HiPC 2019
Performance-driven Programming of Multi-TFLOP Deep Learning Accelerators∗
- Swagath Venkataramani
- Jungwook Choi
- et al.
- 2019
- IISWC 2019
POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators
- Swagath Venkataramani
- Jungwook Choi
- et al.
- 2017
- PACT 2017
Synthesis design strategies for energy-efficient microprocessors
- Ching Zhou
- Yu-Shiang Lin
- et al.
- 2016
- ICCD 2016
A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple
- Suyoung Bang
- Jae-Sun Seo
- et al.
- 2015
- VLSI Circuits 2015
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Circuits 2013
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Technology 2013
A fully anlytical model for carbon nanotube FETs including quantum capacitances and electrostatics
- Lan Wei
- David J. Frank
- et al.
- 2011
- NSTI-Nanotech 2011