Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication ErrorJulian BuchelAthanasios Vasilopouloset al.2023IEEE JESTCS
Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and InferenceManuel Le GalloCorey Liam Lammieet al.2023APL Mach. Learn.
Deep neural network inference with a 64-core in-memory compute chip based on phase-change memoryManuel Le Gallo2023E\PCOS 2023
Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based acceleratorsMalte J. RaschCharles Mackinet al.2023Nature Communications
Deep neural network inference with a 64-core in-memory compute chip based on phase-change memoryManuel Le Gallo2023NVMTS 2023
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inferenceManuel Le GalloRiduan Khaddam-Aljamehet al.2023Nature Electronics
AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory ComputingHadjer BenmezianeCorey Lammieet al.2023EDGE 2023
In-memory computing for accelerating deep neural networks and neuro-vector-symbolic architecturesManuel Le GalloIrem Boybat-Karaet al.2023AICAS 2023
Exploiting the State Dependency of Conductance Variations in Memristive Devices for Accurate In-Memory ComputingAthanasios VasilopoulosJulian Buchelet al.2023IEEE T-ED