Publications

49 results for Scott D. Halle

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005
High-performance circuit design for the RET-enabled 65nm technology node
- - Lars Liebmann
  - Arnold Barish
  - et al.
- 2004
- AMM 2004
A Novel Graded Antireflective Coating with Built-in Hardmask Properties Enabling 65nm and Below CMOS Device Patterning
- - K. Babich
  - N. Fukiage
  - et al.
- 2003
- IEDM 2003
Hardmask technology for sub-100 nm lithographic imaging
- - Katherina Babich
  - Arpan P. Mahorowala
  - et al.
- 2003
- Microlithography 2003
Highly etch selective spin-on bottom antireflective coating for use in 193 nm lithography and beyond
- - Dirk Pfeiffer
  - Arpan Mahorowala
  - et al.
- 2003
- Microlithography 2003
1.5-V single work-function W/WN/n⁺-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM
- - Rajesh Rengarajan
  - Boyong He
  - et al.
- 2002
- IEEE Electron Device Letters
Tunable anti-reflective coatings with built-in hard mask properties facilitating thin resist processing
- - Arpan P. Mahorowala
  - Katherina Babich
  - et al.
- 2001
- Proceedings of SPIE - The International Society for Optical Engineering
When is bilayer thin-film imaging suitable: Comparison with single layer resists
- - Scott Halle
  - Alan Thomas
  - et al.
- 2001
- Proceedings of SPIE - The International Society for Optical Engineering
Plasma-etching processes for ULSI semiconductor circuits
- - M. Armacost
  - P.D. Hoh
  - et al.
- 1999
- IBM J. Res. Dev