LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs
- Minsik Cho
- Hua Xiang
- et al.
- 2013
- ICCAD 2013
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87 results for Ruchir Puri
Network flow based datapath bit slicing
- Hua Xiang
- Minsik Cho
- et al.
- 2013
- ISPD 2013
Intuitive ECO synthesis for high performance circuits
- Haoxing Ren
- Ruchir Puri
- et al.
- 2013
- DATE 2013
Novel binary linear programming for high performance clock mesh synthesis
- Minsik Cho
- David Z. Pan
- et al.
- 2010
- ICCAD 2010
BSM pin assignment with differential pairing on multiple layer designs
- Hua Xiang
- Tingdong Zhou
- et al.
- 2010
- EPEPS 2010
Logical and physical restructuring of fan-in trees
- Hua Xiang
- Haoxing Ren
- et al.
- 2010
- ISPD 2010
The dawn of 22nm era: Design and CAD challenges
- Ruchir Puri
- David S. Kung
- 2010
- VLSID/Embedded 2010
DeltaSyn: An efficient logic difference optimizer for ECO synthesis
- Smita Krishnaswamy
- Haoxing Ren
- et al.
- 2009
- ICCAD 2009
64-bit prefix adders: Power-efficient topologies and design solutions
- Ching Zhou
- Bruce M. Fleischer
- et al.
- 2009
- CICC 2009
A simple fast exact density calculation algorithm
- Hua Xiang
- Chris Chu
- et al.
- 2009
- ICICDT 2009