Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
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6 results for Richard Conti
Effect of in-situ capping on phase change memory device performance : Aepm: Advance equipment processes and materials
- Kevin Brew
- Richard Conti
- et al.
- 2020
- ASMC 2020
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017
Non-poisoning dual damascene patterning scheme for low-k and ultra low-k BEOL
- W. Cote
- D. Edelstein
- et al.
- 2006
- ADMETA 2006
Improved Air Spacer for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- IEEE Transactions on Electron Devices
Temperature distribution in an ideal azimuthally symmetric chemicalvapor-deposition reactor
- David E. Kotecki
- Richard A. Conti
- 1992
- Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films