High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay
- M. Hargrove
- S.W. Crowder
- et al.
- 1998
- IEDM 1998
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7 results for L.K. Han
Electrical characteristics and reliability of sub-3 nm gate oxides grown on nitrogen implanted silicon substrates
- L.K. Han
- S.W. Crowder
- et al.
- 1997
- IEDM 1997
Breakdown measurements of ultra-thin SiO2 at low voltage
- J.H. Stathis
- A. Vayshenker
- et al.
- 2000
- VLSI Technology 2000
Modular 0.13 μm bulk CMOS technology for high performance and low power applications
- L.K. Han
- S. Biesemans
- et al.
- 2000
- VLSI Technology 2000
Challenges for accurate reliability projections in the ultra-thin oxide regime
- E. Wu
- W.W. Abadeer
- et al.
- 1999
- IRPS 1999
Modeling and characterization of n+- and p+-polysilicon-gated ultra-thin oxides (21-26 angstroms)
- S.H. Lo
- D.A. Buchanan
- et al.
- 1997
- VLSI Technology 1997
Ultra-thin oxide reliability for ULSI applications
- Ernest Y. Wu
- James H. Stathis
- et al.
- 2000
- Semiconductor Science and Technology