Statistical timing for parametric yield prediction of digital integrated circuits
- J.A.G. Jess
- K. Kalafala
- et al.
- 2003
- DAC 2003
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3 results for J.A.G. Jess
Foreground memory management in data path synthesis
- Leon Stok
- J.A.G. Jess
- 2006
- International Journal of Circuit Theory and Applications
Statistical timing for parametric yield prediction of digital integrated circuits
- Jochen A. G. Jess
- Kerim Kalafala
- et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems