A self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature
- G.M. Cohen
- C. Cabral Jr.
- et al.
- 2002
- MRS Proceedings 2002
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48 results for R.A. Roy
A self-aligned silicide process for thin silicon-on-insulator MOSFETs and bulk MOSFETs with shallow junctions
- G.M. Cohen
- C. Cabral Jr.
- et al.
- 2001
- MRS Proceedings 2001
New polysilicon disposable sidewall process for sub-50 nm CMOS
- K.L. Lee
- D. Boyd
- et al.
- 2001
- ESSDERC 2001
High performance of planar double gate MOSFETs with thin backgate dielectrics
- E.C. Jones
- M. Ieong
- et al.
- 2001
- DRC 2001
Very high performance 50 nm CMOS at low temperature
- S.J. Wind
- L.T. Shi
- et al.
- 1999
- IEDM 1999
The future of silicide for CMOS contacts
- R.A. Roy
- C. Cabral Jr.
- et al.
- 1999
- MRS Spring Meeting 1999
Is selective CVD an improvement for the titanium silicide process in sub-quarter micron technology? A phase formation study using x-ray diffraction
- R.A. Roy
- Cryil Cabral Jr.
- et al.
- 1998
- MRS Spring Meeting 1998
Is selective CVD an improvement for the titanium silicide process in sub-quarter micron technology? A phase formation study using x-ray diffraction
- R.A. Roy
- Cryil Cabral Jr.
- et al.
- 1998
- MRS Spring Meeting 1998
Low temperature formation of C54-TiSi2 using titanium alloys
- C. Cabral Jr.
- L. Clevenger
- et al.
- 1997
- Applied Physics Letters
Crystallographic texture of C54 titanium disilicide as a function of deep submicron structure geometry
- V. Svilan
- K.P. Rodbell
- et al.
- 1997
- Journal of Electronic Materials