C.K. Wong, Don Coppersmith
Journal of the ACM
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules.
C.K. Wong, Don Coppersmith
Journal of the ACM
C.C. Lee, D.T. Lee, et al.
Acta Informatica
Charles Chiang, Majid Sarrafzadeh, et al.
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
Charles Chiang, Majid Sarrafzadeh, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems