Thermoelectric mapping of nanostrucutres

Abstract

There is intense interest to develop nanowires [1] and superlattices [2] that may offer superior thermoelectric figure of merit for efficient energy conversion. Meanwhile, the advance of semiconductor processing techniques has yielded impurity-doped semiconductor nanostructures with a doped region as small as a few nanometers. These include shallow junction Si field-effect transistors, strained Si/SiGe/Ge heterostructures and quantum dots, III-V heterostructures, and doped nanowires and nanotubes. Due to various size confinement effects, these doped semiconductor nanostructures often have unique electrical, optoelectronic, or thermoelectric properties that may lead to a wide range of applications. In contrast to the progress made in synthesizing thermoelectric nanostructures and in fabricating doped semiconductor nanostructures, the ability to quantify thermoelectric property and carrier concentration in comparable length scale has been lagging behind. For example, the 1997 U.S. Roadmap of Semiconductors from the Semiconductor Industry Association (SIA) defines the need for nanometer-scale measurements of carrier concentration profiles [3]. Though progress has been made, currently no technique can satisfy the requirements posted by the SIA roadmap due to the lack of either spatial resolution or accuracy.