Publication
SISPAD 2017
Conference paper

The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs

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Abstract

Fabricated InAs/Si and InAs/GaAsSb vertical nanowire tunnel FETs are analyzed by physics-based TCAD with emphasis on the impact of hetero-junction and oxide-interface traps on their performance. After careful fitting of a minimum set of parameters, the effects of diameter scaling and gate alignment are predicted. Trap-assisted tunneling at the oxide interface is suppressed by scaling the diameter into the volume-inversion regime. Gate alignment steepens the slope and increases the ON-current. The 'trap-tolerant' device geometry can result in a small sub-threshold swing despite commonly present trap concentrations.

Date

25 Oct 2017

Publication

SISPAD 2017

Authors

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