The impact of device scaling limits

Abstract

The semiconductor market has been experiencing remarkable expansion, with a CGR approaching 30% over the last half decade. This growth has been driven by continuing device miniaturization and the attendant increase in integration level and performance and decrease in cost. However, as devices become smaller, there is concern that fundamental limits will restrict further progress. Possible fundamental limits to device miniaturization and chip performance are considered. It is shown that while there are such limits, devices into the deep sub-0.1 mm region with acceptable characteristics could be built, providing that practical considerations in such areas as fabrication and lithography, design complexity, interconnect delay and fabrication facility cost can be overcome.