Publication
IEEE T-ED
Paper

The Design and Optimization of High-Performance, Double-Poly Self-Aligned p-n-p Technology

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Abstract

This paper describes the device design and performance of a double-poly self-aligned p-n-p technology, featuring a low-resistivity p<sup>+</sup> subcollector, thin p-epi, and boron-doped poly-emitter. Device isolation was provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (≥40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm, and base widths less than 100 nm were obtained. Cut-off frequencies up to 27 GHz were obtained, and the ac performance was demonstrated by an NTL-gate delay of 36 pS, and an active-pull-down (APD) ECL-gate delay of 20 pS. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. Thus the matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits. © 1991 IEEE

Date

01 Jan 1991

Publication

IEEE T-ED

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