The design and implementation of double-precision multiplier in a first-generation CELL processor

Abstract

We present the double precision multiplier for a 90nm PD-SOI first-generation CELL processor. Dynamic Booth logic is designed for scalability and with noise, leakage, and pulse width variation tolerance. Static partial product compression is implemented with replicated bits for performance. The design supports fine-grained clock gating domains for active power reduction. © 2005 IEEE.