Technology and power-speed trade-offs in quantum-dot and nano-crystal memory devices

Abstract

The necessary design trade-offs in oxide, channel, and storage-dot dimensions quantum dot and nanocrystal Flash single-element memories with respect to write and erase speeds, retention time, and power, are demonstrated by using measured room temperature characteristics and self-consistent calculations to study the technology-performance concerns for the practical use of these memories. These memories offer great advantage in scalability, ease of fabrication, logic integration, and flexibility. By tuning the gate structure, a variety of trade-offs between speed, power, and retention are achieved.