Surface-tension-driven multi-chip self-alignment techniques for heterogeneous 3D integration

Abstract

Surface-tension-driven self-alignment (SA) is a promising technique for heterogeneous die-level stacking. Multiple dies can be manipulated in parallel at minimal cost. A defined amount of water present between the die and a carrier substrate is used to align the components. The minimization of the water-air interface is the driving force. Most studies were performed with a completely wetted chip surface with a resulting alignment of die periphery to carrier. This achieves a maximal die-pad to carrier-pad alignment quality equal to the dicing accuracy, which is typically 25 um. To further improve the pad-to-pad alignment accuracy, we propose a pad-assisted SA technique. With an initial placement quality of less than half a pad pitch, this technique achieves submicron SA accuracy. Furthermore, we extend the process to dies with Au studs needed in later thermo-compression bonding. Design rules to design a stable process are reported. A meniscus minimization model is built, which explains the experimental results and helps to design new SA patterns. © 2011 IEEE.