About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
ISSCC 1978
Conference paper
Sub-100ps experimental Josephson interferometer logic
Abstract
This paper will cover experimental Josephson interferometer logic gates fabricated in a 5 μm technology with 1 μW/gate dissipation, citing measured delays of 40, 95 and 120ps for OR, AND and master slave latch, respectively.