Publication
Solid State Electronics
Paper

Simulations of collector resistance of pnp transistors for complementary bipolar technology

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Abstract

This paper describes simulation results for the collector resistance of a vertical pnp for complementary bipolar LSI, which can be fabricated by adding a p-well formation to the npn process[1]. It is found that the performance fT and current driving capability of such pnp devices are limited by the collector resistance Rc. A simple method for extracting the lumped Rc from a device simulator is described. The simulations show that the collector charging time adds a significant amount to emitter-to-collector delay, and the quasi-saturation in the collector junction limits its current driving capability. These observations highlight the importance of collector design in high performance pnp. © 1989.

Date

01 Jan 1989

Publication

Solid State Electronics

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