Simulation of coupling capacitances using matrix partitioning

Abstract

This paper presents a matrix partitioning scheme for the simulation of coupling capacitances in timing and noise analysis. An error criterion similar to the local truncation error of integration algorithms was developed to control the error due to this matrix partitioning algorithm. The major advantage of the algorithm is that it does not require iterations such as required in relaxation algorithms, and it is designed to work with circuit partitioning for efficient simulation of large circuits in fast circuit/timing simulator like ACES, which forms the basis for an efficient transistor level simulation and analysis. The matrix partitioning algorithm also fits well with controlled explicit integration algorithms. Results demonstrate that the algorithm can ensure simulation accuracy without significantly degrading simulation efficiency for the timing and noise analysis of circuits designed in advanced technologies with small feature sizes.