Conference paper

Silicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver


The design, fabrication, assembly and characterization of a silicon carrier package used for enabling a Tb/s parallel optical transceiver is reported. A hierarchical approach involving eutectic AuSn and SnPb solder systems and flip chip bonding technology is used to assemble the transceiver module. The measurement and model for alignment tolerance analysis shows constant coupling efficiency from the optoelectronics (OE) devices to waveguide over a range of ± 10 μm, giving an excellent margin for alignment. Electrical simulations and measurement of silicon carrier through-vias shows an insertion loss of better than 1 dB at 20 GHz. Simulations and measurements also exhibit an attenuation of 4.3 dB/cm at 20 GHz for high speed wiring on the silicon carrier, which is adequate for 20 Gbps data transmission over a length of 7 mm. © 2006 Materials Research Society.