H.-S. Wong
IEDM 1997
In this paper, we report a fabrication method that attains the `ideal' double-gate MOSFET device structure. The top and bottom gates are inherently self-aligned to the source/drain. The source/drain is a fanned-out source/drain structure, which provides a low parasitic resistance. Channel silicon thickness is determined by a planar film deposition process with good uniformity control in principle. N-channel double-gate MOSFET's with a 25 nm thick silicon channel were successfully demonstrated.
H.-S. Wong
IEDM 1997
E. Burstein
Ferroelectrics
A.B. McLean, R.H. Williams
Journal of Physics C: Solid State Physics
Biancun Xie, Madhavan Swaminathan, et al.
EMC 2011