Recent Advances in Ultra-High-Speed Wireline Receivers with ADC-DSP-Based Equalizers

Abstract

High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100 Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX) including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This paper overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks such as analog front-end (AFE), DSP techniques and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy-and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based SerDes simulation and real-time emulation systems for rapid architecture and design verification are reviewed.