Erik Altman, Jovan Blanusa, et al.
NeurIPS 2023
This paper covers the recent developments of high speed, t 100Gb/s, VCSELs and VCSEL-based transceivers that are designed for co-packaging on a first level package with ASICs, such as CPUs, GPUs, and data center switches.
Erik Altman, Jovan Blanusa, et al.
NeurIPS 2023
Pavel Klavík, A. Cristiano I. Malossi, et al.
Philos. Trans. R. Soc. A
Ronald Fagin
Journal of the ACM
Conrad Albrecht, Jannik Schneider, et al.
CVPR 2025