Processor Clock Generation, Distribution, and Clock Sensor/Management Loops

Abstract

This discussion of processor global clocking starts with on-chip transmission-line effects, and the design and tuning of standard trees, including power, clock gating, and useful skew. Most high performance processors use more specialized methods including clock spines and meshes, which require special timing methods, but can have significant advantages with respect to skew, robustness, and design closure. The design of resonant meshes with mode-changing capabilities are discussed. The final topic is clock sensors and control loops to improve power and performance including useful jitter.