A mask reuse methodology for reducing system-on-a-chip cost
Subhrajit Bhattacharya, John Darringer, et al.
ISQED 2005
The analysis and simulation of effects Induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the timing aspects of Interconnects, power consumption is also important. In this paper, the power distribution analysis of interconnects is studied using a reduced order model. The relation between power consumption and the poles and residues of a transfer function (either exact or approximated) is derived, and a simple yet accurate driver model is developed, allowing power consumption to be computed efficiently. Application of the proposed method to RC networks is demonstrated using a prototype tool.
Subhrajit Bhattacharya, John Darringer, et al.
ISQED 2005
Insup Shin, Jae-Joon Kim, et al.
ISLPED 2013
Insup Shin, Jae-Joon Kim, et al.
IEEE Transactions on VLSI Systems
Xin Zhang, Po-Hung Chen, et al.
IEEE JSSC