Parallel waveform relaxation of circuits with global feedback loops

Abstract

Feedback loops often severely degrade the performance of waveform relaxation techniques in solving large circuit analysis problems. Several new approaches have been studied in this investigation to provide greater parallelism and faster convergence for such circuits. WR-V256, an experimental waveform-relaxation-based parallel circuit simulator for the Victor family of distributed memory parallel machines, was used to study performance tradeoffs of partitioning and scheduling algorithms for circuits containing global feedback loops. This investigation includes circuits ranging from less than 300 to over 93,000 transistors. Several of the circuits were extracted directly from a 16 Mbit DRAM design.