Optimizing history effects in 65nm PD-SOI CMOS

Abstract

History effects in 65-nm partially-depleted Silicon-on-Insulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit designs. ©2006 IEEE.